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complete, dual, 12 - /14 - /16 - bit, serial input, unipolar/bi polar, voltage output dac s ad5722/ad5732/AD5752 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsib ility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.an alog.com fax: 781.461.3113 ? 2008 analog devices, inc. all rights reserved. features complete , dual , 12- /14 - /16 - bit digital - to - analog converter (dac) operates from s ingle/ d ual supplies software programmable output range + 5 v, + 10 v, + 10.8 v, 5 v, 10 v, 10.8 v inl error : 16 lsb maximum, dnl error: 1 lsb max imum total u nadjuste d e rror (tue) : 0.1% fsr max imum settling time: 10 s typ ical integrated reference buffers output control during power - up/brownout simultaneous updating via ldac asynchronous clr applications to zero scale or midscale dsp - /m icrocontroller - compatible serial interface 24- l ead tssop operating temperature range: ? 40 c to +85 c i cmos p rocess t echnology 1 industrial automation closed - loop servo control, process control automotive test and measurement programmable logic c ontrollers general description the ad5722/ad5732/AD5752 are dual , 12- /14 - /16 - bit , serial input, voltage output , digital - to - analog converters . they operate from single - supply voltages from + 4.5 v up to + 16.5 v or dual - supply v oltages from 4.5 v up to 1 6.5 v. nominal full - scale output range is software - s electable from + 5 v, + 10 v, + 10.8 v, 5 v, 10 v, or 10.8 v. i ntegrated output amplifiers, reference buffers , and proprietary power - up/power - down control circuitry are also provided. the parts offer gua ranteed monotonicity, integral nonlin earity (inl) of 16 lsb max imum , low noise , and 10 s typical settling time . the ad5722/ad5732/AD5752 use a serial interface that operates at clock rates up to 30 mhz and are compatible with dsp and microcontroller inte rface standards. double buffering allows the simultaneous updating of all dacs. the input coding is user - selectable twos complement or offset binary for a bipolar output (depending on the state of pin bin/ 2scomp the ad5722/ad5732/AD5752 are pin compatible with the ) , and straight binary for a unipolar output. the asynchronous clear function clears all dac registers to a user - s electable zero - scale or mid scale output. the parts are available in a 24 - lead tssop and offer guaranteed specifications over the ? 40c to +85c industrial temperatu re range. ad5724 / ad5734 / ad5754 , which are complete, quad, 12 - /14 - / 16- bit, serial input, unipolar/bipolar voltage output dacs. functional block dia gram d a c b i n p u t register a i n p u t register b d a c a l d a c r e f i n v out b v out a reference buffers s d i n s c l k s y n c s d o d v cc g n d d a c _ g n d (2) s ig _ g n d (2) ad5722/ad5732/AD5752 i n p u t s h i f t r e g i s t e r a n d c o n t r o l l og i c av dd av ss dac register a dac register b c l r b i n / 2s c o m p 06467-001 12/14/ 1 6 12/14/ 1 6 12/14/ 1 6 figure 1. 1 for analog systems designers within industrial/instrumentation equipment oems who need high performance ics at higher voltage levels, i cmos ? is a technology platform that enables the development of analog ics capable of 30 v and operating at 15 v supplies while allowing dramatic reductions in power consumption and package size, as well as increased ac and dc performance.
ad5722/ad5732/AD5752 rev. 0 | page 2 of 32 table o f contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac performance characteristics ................................................ 5 timing characteristics ................................................................ 5 timing diagrams .......................................................................... 6 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 10 terminology .................................................................................... 16 theory of operation ...................................................................... 18 architecture ................................................................................. 18 serial interface ............................................................................ 18 load dac ( ldac asynchronous clear ( ) ..................................................................... 20 clr configuring the ad5722/ad5 732/AD5752 .......................... 20 ) ....................................................... 20 transfer function ....................................................................... 20 input shift register .................................................................... 24 dac r egister .............................................................................. 25 output range select register ................................................... 25 control register ......................................................................... 26 p ower control register .............................................................. 26 design features ............................................................................... 27 analog output control ............................................................. 27 power - down mode .................................................................... 27 overcurrent protection ............................................................. 27 thermal shutdown .................................................................... 27 applications information .............................................................. 28 +5 v/5 v operation ................................................................ 28 layout guidelines ....................................................................... 28 galvanically isolated interface ................................................. 28 voltage reference selection ...................................................... 28 microprocessor interfacing ....................................................... 29 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision h istory 10/ 08 revision 0: initial version
ad5722/ad5732/AD5752 rev. 0 | page 3 of 32 specifications av dd = 4.5 v 1 1 to 16.5 v ; av ss = ?4.5 v to ? 16.5 v , or av ss = 0 v ; gnd = 0 v ; refin = 2.5 v ; dv cc = 2.7 v to 5.5 v ; r load = 2 k ? ; c l oad = 200 pf ; a ll specifications t min to t max , unless otherwise noted. table 1 . parameter min ty p max unit test conditions/comments accuracy outputs unloaded resolution AD5752 16 bits ad5732 14 bits ad5722 12 bits total unadjusted error (tue) b version ?0.1 + 0.1 % fsr a version ? 0.3 +0.3 % fsr integral nonlineari ty (inl) 2 AD5752 a , b version s ? 16 + 16 lsb ad5732 a version ? 4 + 4 lsb ad5722 a version ? 1 + 1 lsb differential nonlinearity (dnl) ? 1 + 1 lsb all models, all versions, guaranteed monotonic bipolar zero error ? 6 + 6 mv t a = 25c, error at other temperatures obtained using bipolar zero tc bipolar zero tc 3 4 ppm fsr/c zero - scale error ?6 +6 mv t a = 25c, error at other temperatures obtained using zero - scale tc zero - scale tc 3 4 ppm fsr/c of fset error ? 6 + 6 mv t a = 25c, error at other temperatures obtained using zero - scale tc offset error tc 4 ppm fsr/c gain error ? 0.0 25 + 0.025 % fsr 10 v r ange, t a = 25c, error at other temperatures obtained using gain tc gain error 3 ?0.065 0 +10 v and +5 v r anges, t a = 25c, error at other temperatures obtained using gain tc gain error 3 0 +0.08 5 v r ange, t a = 25c, error at other temperatures obtained using gain tc gain tc 3 4 ppm fsr/c dc crosstalk 3 120 v reference input 3 reference input voltage 2.5 v 1% for specified performance dc input impedance 1 5 m ? input current ?2 0.5 +2 a reference range 2 3 v output characteristics 3 output voltage range ?10.8 +10.8 v av dd /av ss = 11.7 v min, refin = +2.5 v ?12 +12 v av dd /av ss = 12.9 v min, refin = +3 v head room required 0.5 0.9 v output voltage tc 4 ppm fsr/c output voltage drift vs. time 50 ppm fsr drift after 1000 hours of lifetest @ 125c short - circuit current 20 ma load 2 k ? for specified performance capacitive load stability 4000 pf dc output impedance 0.5 ?
ad5722/ad5732/AD5752 rev. 0 | page 4 of 32 parameter min ty p max unit test conditions/comments digital inputs 3 dv cc = 2.7 v to 5.5 v, jedec compliant input high voltage, v ih 2 v input low voltage, v il 0.8 v input current 1 a per pin pin capacitance 5 pf per pin digital outputs (sdo) 3 output low voltage, v ol 0.4 v dv cc = 5 v 10%, sinking 200 a output high voltage, v oh dv cc ? 1 v dv cc = 5 v 10%, sourcing 200 a output low voltage, v ol 0.4 v dv c c = 2.7 v to 3.6 v, sinking 200 a output high voltage, v oh dv cc ? 0.5 v dv cc = 2.7 v to 3.6 v, sourcing 200 a high impedance leakage current ?1 +1 a high impedance output capacitance 5 pf power requirements av dd 4.5 16.5 v av ss ?4.5 ?16.5 v dv cc 2.7 5.5 v power supply sensitivity 3 ?v out / ? v dd ?65 db ai dd 3.25 ma/channel outputs unloaded 2. 4 ma/channel av ss = 0 v, outputs unloaded ai ss 2.5 ma/channel outputs unloa ded di cc 0.5 3 a v ih = dv cc , v il = gnd power dissipation 190 mw 16.5 v operation, outputs unloaded 7 9 mw 16.5 v operation, av ss = 0 v, outputs unloaded power - down currents ai dd 4 0 a ai ss 40 a d icc 300 n a 1 for specified performance , the maximum headroom requirement is 0.9 v. 2 inl is the relative accuracy. it is measured from code 512, code 128, and code 32 for the AD5752, the ad5732, and the ad5722, respectively. 3 guaranteed by characterization; not production tested.
ad5722/ad5732/AD5752 rev. 0 | page 5 of 32 ac performance characteristics av dd = 4.5 v 1 to 16.5 v; av ss = ?4.5 v to ?16.5 v, or av ss = 0 v; gnd = 0 v; refin = 2.5 v; dv cc = 2.7 v to 5.5 v; r load = 2 k; c load = 200 pf; all specifications t min to t max , unless otherwise noted. table 2. parameter 2 min typ max unit test conditions/comments dynamic performance output voltage settling time 10 12 s 20 v step to 0.03% fsr 7.5 8.5 s 10 v step to 0.03% fsr 5 s 512 lsb step se ttling (16-bit resolution) slew rate 3.5 v/s digital-to-analog glitch energy 13 nv-sec glitch impulse peak amplitude 35 mv digital crosstalk 10 nv-sec dac-to-dac crosstalk 10 nv-sec digital feedthrough 0.6 nv-sec output noise 0.1 hz to 10 hz bandwidth 15 v p-p 0x8000 dac code 100 khz bandwidth 80 v rms output noise spectral density 320 nv/hz measured at 10 khz, 0x8000 dac code 1 for specified performan ce, the maximum headroom requirement is 0.9 v. 2 guaranteed by design and characterization; not production tested. timing characteristics av dd = 4.5 v to 16.5 v; av ss = ?4.5 v to ?16.5 v, or av ss = 0 v; gnd = 0 v; refin = 2.5 v; dv cc = 2.7 v to 5.5 v; r load = 2 k; c load = 200 pf; all specifications t min to t max , unless otherwise noted. table 3. parameter 1, 2, 3 limit at t min , t max unit description t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 13 ns min sclk falling edge to sync rising edge t 6 100 ns min minimum sync high time (write mode) t 7 5 ns min data setup time t 8 0 ns min data hold time t 9 20 ns min ldac falling edge to sync falling edge t 10 20 ns min sync rising edge to ldac falling edge t 11 20 ns min ldac pulse width low t 12 10 s max dac output settling time t 13 20 ns min clr pulse width low t 14 2.5 s max clr pulse activation time t 15 4 13 ns min sync rising edge to sclk falling edge t 16 4 40 ns max sclk rising edge to sdo valid (c l sdo 5 = 15 pf) t 17 200 ns min minimum sync high time (readback/daisy-chain mode) 1 guaranteed by characterization; not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of dv cc ) and timed from a voltage level of 1.2 v. 3 see figure 2, figure 3, and figure 4. 4 daisy-chain and readback mode. 5 c l sdo = capacitive load on sdo output.
ad5722/ad5732/AD5752 rev. 0 | page 6 of 32 timing diagrams 06467-002 d b 2 3 s c l k s y n c s d i n l d a c c l r v out x v out x v out x 4 2 2 1 d b 0 t 1 2 t 1 2 t 1 0 t 1 1 t 1 4 t 1 3 t 9 t 8 t 7 t 4 t 6 t 3 t 2 t 1 t 5 figure 2 . serial interface timing diagram 06467-003 t 4 t 10 t 16 t 8 t 7 t 11 t 3 t 2 t 5 t 1 t 15 ldac sdo sdin sync sclk 8 4 4 2 d0b d32b d0b d32b db23 input word for dac n undefined input word for dac n ? 1 input word for dac n db0 t 17 figure 3 . daisy - chain timing diagram
ad5722/ad5732/AD5752 rev. 0 | page 7 of 32 sdo sdin sync sclk 24 24 db23 db0 db23 db0 selected register data clocked out undefined nop condition input word specifies register to be read 1 1 db23 db0 db23 db0 t 17 06467-004 figure 4 . readback timing diagram
ad5722/ad5732/AD5752 rev. 0 | page 8 of 32 absolute maximum rat ings t a = 25c unless otherwise noted. transie nt currents of up to 100 ma do not cause scr latch - up. table 4 . parameter rating av dd to gnd ? 0.3 v to +17 v av ss to gnd +0.3 v to ? 17 v dv cc to gnd ? 0.3 v to +7 v digital inputs to gnd ? 0.3 v to dv cc + 0.3 v or 7 v (whichever is less) digital outputs to gnd ? 0.3 v to dv cc + 0.3 v or 7 v (whichever is less) ref in to gnd ? 0.3 v to +5 v v out a or v out b to gnd av ss to av dd dac_gnd to gnd ? 0.3 v to +0.3 v sig_gnd to gnd ? 0.3 v to +0.3 v operating temperature range , t a industr ial ? 40c to +85c storage temperature range ? 65c to +150c junction temperature, t j max 105c 24- lead tssop package ja thermal impedance 42 c/w jc thermal impedance 9c/w power dissipation (t j max ? t a )/ ja lead temperature jedec industry stan dard soldering j - std -020 esd (human body model) 3.5 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditi ons above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5722/ad5732/AD5752 rev. 0 | page 9 of 32 pin configuration and fu nction descriptions 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad5722/ ad5732/ AD5752 clr ldac av ss nc v out a nc sync nc bin/2scomp gnd sdo refin sig_gnd sclk sdin nc av dd v out b nc sig_gnd dac_gnd dac_gnd dv cc nc top view (not to scale) 06467-005 notes 1. nc = no connect 2. it is recommended that the exposed pad be thermally connected to a copper plane for enhanced thermal performance. figure 5. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 av ss negative analog supply. voltage ranges from ?4.5 v to ?16.5 v. this pin can be connected to 0 v if output ranges are unipolar. 2, 4, 6, 12, 13, 22 nc do not connect to these pins. 3 v out a analog output voltage of dac a. the output amplifier is capable of directly driving a 2 k, 4000 pf load. 5 bin/2scomp determines the dac coding for a bipolar output range. this pin should be hardwired to either dv cc or gnd. when hardwired to dv cc , input coding is offset binary. when ha rdwired to gnd, input coding is twos complement. (for unipolar output ranges, coding is always straight binary.) 7 sync active low input. this is the frame synchronization signal for the serial interface. while sync is low, data is transferred on the falling edge of sclk. data is latched on the rising edge of sync . 8 sclk serial clock input. data is clocked in to the shift register on the falling edge of sclk. this operates at clock speeds up to 30 mhz. 9 sdin serial data input. data must be valid on the falling edge of sclk. 10 ldac load dac, logic input. this is used to update the dac registers and, consequently, the analog outputs. when this pin is tied permanently low, the addressed dac register is updated on the rising edge of sync . if ldac is held high during the write cycle, the dac input register is updated, but the output up date is held off until the falling edge of ldac . in this mode, all analog outputs can be up dated simultaneously on the falling edge of ldac . the ldac pin should not be left unconnected. 11 clr active low input. asserting this pin sets the dac registers to zero-scale code or midscale code (user-selectable). 14 dv cc digital supply. voltage ranges from 2.7 v to 5.5 v. 15 gnd ground reference. 16 sdo serial data output. used to clock data from the serial register in daisy-chain or readback mode. data is clocked out on the rising edge of sclk and is valid on the falling edge of sclk. 17 refin external reference voltage input. reference input range is 2 v to 3 v. refin = 2.5 v for specified performance. 18, 19 dac_gnd ground reference for the two digital-to-analog converters (dacs). 20, 21 sig_gnd ground reference for the two output amplifiers. 23 v out b analog output voltage of dac b. the output amplifier is capable of directly driving a 2 k, 4000 pf load. 24 av dd positive analog supply. voltage ranges from 4.5 v to 16.5 v. 25 (epad) exposed paddle (epad) negative analog supply connection. voltage ranges from ?4.5 v to ?16.5 v. this paddle can be connected to 0 v if output ranges are unipolar. the paddle can be le ft electrically unconnected provided that a supply connection is made at the av ss pin. it is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance.
ad5722/ad5732/AD5752 rev. 0 | page 10 of 32 typical performance characteristics code inl error (lsb) 0 10,000 20,000 30,000 40,000 50,000 60,000 ?8 ?6 ?4 ?2 0 2 4 6 av dd /av ss = +12v/0v, range = +10v av dd /av ss = 12v, range = 10v av dd /av ss = 6.5v, range = 5v av dd /av ss = +6.5v/0v, range = +5v 06467-013 figure 6. AD5752 integral nonlinear ity error vs. code ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 code inl error (lsb) av dd /av ss = +12v/0v, range = +10v av dd /av ss = 12v, range = 10v av dd /av ss = 6.5v, range = 5v av dd /av ss = +6.5v/0v, range = +5v 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 06467-014 figure 7. ad5732 integr al nonlinearity error vs. code ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0 500 1000 1500 2000 2500 3000 3500 4000 code inl error (lsb) av dd /av ss = +12v/0v, range = +10v av dd /av ss = 12v, range = 10v av dd /av ss = 6.5v, range = 5v av dd /av ss = +6.5v/0v, range = +5v 06467-015 figure 8. ad5722 integral nonlinearity error vs. code code dnl error (lsb) av dd /av ss = +12v/0v, range = +10v av dd /av ss = 12v, range = 10v av dd /av ss = 6.5v, range = 5v av dd /av ss = +6.5v/0v, range = +5v 0 10,000 20,000 30,000 40,000 50,000 60,000 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 06467-016 figure 9. AD5752 differential nonlinearity error vs. code ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 code dnl error (lsb) av dd /av ss = +12v/0v, range = +10v av dd /av ss = 12v, range = 10v av dd /av ss = 6.5v, range = 5v av dd /av ss = +6.5v/0v, range = +5v 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 06467-017 figure 10 . ad5732 differenti al nonlinearity error vs. code ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0 500 1000 1500 2000 2500 3000 3500 4000 av dd /av ss = +12v/0v, range = +10v av dd /av ss = 12v, range = 10v av dd /av ss = 6.5v, range = 5v av dd /av ss = +6.5v/0v, range = +5v code dnl error (lsb) 06467-018 figure 11 . ad5722 differenti al nonlinearity error vs. code
ad5722/ad5732/AD5752 rev. 0 | page 11 of 32 temperature ( c) inl error (lsb) ?8 ?6 ?4 ?2 0 2 4 6 8 ?40 ?20 0 20 40 60 80 max inl 10v max inl 5v min inl 10v min inl 5v max inl +10v min inl +10v max inl +5v min inl +5v 06467-044 figure 12 . AD5752 integral nonlinearity err or vs. temperature ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 temperature ( c) dnl error (lsb) ?40 ?20 0 20 40 60 80 max dnl 10v max dnl 5v min dnl 10v min dnl 5v max dnl +10v min dnl +10v max dnl +5v min dnl +5v 06467-045 figure 13 . AD5752 differential nonl inearity error vs. temperature ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 supply voltage (v) inl error (lsb) 11.5 12.5 12.0 13.5 14.0 13.0 14.5 15.0 15.5 16.0 16.5 bipolar 10v min unipolar 10v min bipolar 10v max unipolar 10v max 06467-034 figure 14 . AD5752 integral nonline arity error vs. supply voltage supply voltage (v) 5.5 8.5 6.5 7.5 10.5 11.5 9.5 12.5 13.5 14.5 15.5 16.5 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 inl error (lsb) bipolar 5v min unipolar 5v min bipolar 5v max unipolar 5v max 06467-035 figure 15 . AD5752 integral nonlinearity error vs. supply v oltage supply voltage (v) dnl error (lsb) 11.5 12.5 12.0 13.5 14.0 13.0 14.5 15.0 15.5 16.0 16.5 0 0.6 0.4 0.2 1.0 0.8 ?0.6 ?0.4 ?0.2 ?1.0 ?0.8 bipolar 10v min unipolar 10v min bipolar 10v max unipolar 10v max 06467-032 figure 16 . AD5752 differential nonline arity error vs. supply voltage supply voltage (v) dnl error (lsb) 5.5 8.5 6.5 7.5 10.5 11.5 9.5 12.5 13.5 14.5 15.5 16.5 0 0.6 0.4 0.2 1.0 0.8 ?0.6 ?0.4 ?0.2 ?1.0 ?0.8 bipolar 5v min unipolar 5v min bipolar 5v max unipolar 5v max 06467-033 figure 17 . AD5752 differential nonlinearity error vs. supply voltag e
ad5722/ad5732/AD5752 rev. 0 | page 12 of 32 supply voltage (v) 11.5 12.5 12.0 13.5 14.0 13.0 14.5 15.0 15.5 16.0 16.5 bipolar 10v min unipolar 10v min bipolar 10v max unipolar 10v max tue (%) ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 06467-036 figure 18 . AD5752 total unadjusted error vs. supply voltage supply voltage (v) 5.5 8.5 6.5 7.5 10.5 11.5 9.5 12.5 13.5 14.5 15.5 16.5 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 tue (%) bipolar 5v min unipolar 5v min bipolar 5v max unipolar 5v max 06467-037 figure 19 . AD5752 total unadjusted error vs. supply voltage ?4 ?3 ?2 ?1 0 1 2 3 4 5 4.5 6.5 8.5 10.5 12.5 14.5 16.5 av dd /av ss (v) ai dd /ai ss (ma) 06467-038 ai dd (ma) ai dd (ma) figure 20 . supply current vs. supply voltage (dual supply) av dd (v) ai dd (ma) 2.0 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 4.5 6.5 8.5 10.5 12.5 14.5 16.5 06467-042 figure 21 . su pply current vs. supply voltage (single supply) ?3 ?2 ?1 0 1 2 3 4 temperature ( c) zero-scale error (mv) ?40 ?20 0 20 40 60 80 10v 5v +10v 06467-046 figure 22 . zero - scale err or vs. temperature ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 temperature ( c) bipolar zero error (mv) ?40 ?20 0 20 40 60 80 5v range 10v range 06467-047 figure 23 . bipolar zero error vs. temperature
ad5722/ad5732/AD5752 rev. 0 | page 13 of 32 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 10v 5v +10v temperature ( c) gain error (% fsr) ?40 ?20 0 20 40 60 80 06467-048 figure 24 . gain err or vs. te mperature v logic (v) di cc ( a) ?100 0 100 200 300 400 500 600 700 800 900 1000 0 1 2 3 4 5 6 dv cc = 5v dv cc = 3v 06467-043 figure 25 . digital current vs. logic input voltage output current (ma) output voltage delta (v) ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 5v range, code = 0xffff 10v range, code = 0xffff +10v range, code = 0xffff +5v range, code = 0xffff 5v range, code = 0x0000 10v range, code = 0x0000 06467-040 figure 26 . output source and sink capabilit y ?15 ?10 ?5 0 5 10 15 ?3 ?1 1 3 5 7 9 11 06467-022 time (s) output voltage (v) figure 27 . full - scale settling time , 10 v range ?7 ?5 ?3 ?1 1 3 5 7 ?3 ?1 1 3 5 7 9 11 06467-023 time (s) output voltage (v) figure 28 . full - scale settling time , 5 v range 0 2 4 6 8 10 12 ?3 ?1 1 3 5 7 9 11 06467-024 time (s) output voltage (v) figure 29 . full - scale settling time , + 10 v range
ad5722/ad5732/AD5752 rev. 0 | page 14 of 32 0 1 2 3 4 5 6 ?3 ?1 1 3 5 7 9 11 06467-025 time (s) output voltage (v) figure 30 . full - scale settling time , +5 v range time (s) output voltage (v) ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 ?1 0 1 2 3 4 5 10v range, 0x7fff to 0x8000 10v range, 0x8000 to 0x7fff 5v range, 0x7fff to 0x8000 5v range, 0x8000 to 0x7fff +10v range, 0x7fff to 0x8000 +10v range, 0x8000 to 0x7fff +5v range, 0x7fff to 0x8000 +5v range, 0x8000 to 0x7fff 06467-039 figure 31 . digital - to- analog glitch energy ch1 5v m 5s line 73.8v 1 range = +10v range = 10v range = 5v range = +5v 06467-026 figure 32 . peak - to - peak noise, 0.1 hz to 10 hz bandwidth ch1 5v m5s line 73.8v 1 range = +10v range = 10v range = 5v range = +5v 06467-027 figure 33 . peak - to - peak noise, 100 khz bandwidth time (s) output voltage (v) ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 ?50 ?30 ?10 10 30 50 70 90 av dd /av ss = 16.5v av dd = +16.5v, avss = 0v 06467-041 figure 34 . output glitch on power - up 06467-019 code tue (lsb) ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 0 1000 2000 3000 4000 5000 6000 av dd /av ss = +12v/0v, range = +10v av dd /av ss = 12v, range = 10v av dd /av ss = 6.5v, range = 5v av dd /av ss = +6.5v/0v, range = +5v figure 35 . AD5752 total unadjusted error vs. code
ad5722/ad5732/AD5752 rev. 0 | page 15 of 32 ?10 ?8 ?6 ?4 ?2 0 2 4 0 2000 4000 6000 8000 10000 12000 14000 16000 06467-020 code tue (lsb) av dd /av ss = +12v/0v, range = +10v av dd /av ss = 12v, range = 10v av dd /av ss = 6.5v, range = 5v av dd /av ss = +6.5v/0v, range = +5v figure 36 . ad5732 total unadjusted error vs. code ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 0 500 1000 1500 2000 2500 3000 3500 4000 06467-021 code tue (lsb) av dd /av ss = +12v/0v, range = +10v av dd /av ss = 12v, range = 10v av dd /av ss = 6.5v, range = 5v av dd /av ss = +6.5v/0v, range = +5v figure 37 . ad5722 total unadjusted error vs. code
ad5722/ad5732/AD5752 rev. 0 | page 16 of 32 ter minology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy , or integral nonlinearity , is a m easure of the maximum deviation in lsbs from a straight line passing through the endpoints of the dac transfer function. a typical in l vs. code plot can be seen in figure 6 . differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 9 . monotonicity a dac is monotonic if the output either increases or remains con stant for increasing digital input code. the ad5722/ ad5732/AD5752 are monotonic over their full operating temperature range. bipolar zero error bipolar z ero error is the deviation of the analog output from the ideal half - scale output of 0 v when the dac r egister is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complemen t coding). a plot of bipolar zero error vs. temperature can be seen in figure 23. bipolar zero tc bipolar z ero tc is a measure of the change in the bipolar zero error with a change in temperature. it is expressed in ppm fsr/c. zero - scale error or negative full - scale error zero - scale error is the error in the dac output voltage when 0x0000 (straight binary coding) or 0x8000 (twos complement coding) is loaded to the dac register. ideally, the output voltage should be negative full - scale ? 1 lsb. a plot of zero - scale error vs. temperature can be seen in figure 22. zero - scale tc zero - scale tc is a measure of the change in zero - scale error with a change in temperature. zero - s cale tc is expressed in ppm fsr/c. ou tput voltage settling time output voltage settling time is the amount of time required for the output to settle to a specified level for a full - scale input change . a plot for full - scale settling time can be seen in figure 27. slew rate the slew rate of a device is a limitation in the rate of change of the output voltage. the ou tput slewing speed of a voltage output dac is usually limited by the slew rate of the amplifier used at its output. slew rate is measured from 10% to 90% of the output signal and is given in v/s. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal and is expressed in % fsr. a plot of gain error vs. temperature can be seen in figure 24. gain tc gain tc is a measure of the change in gain error with changes in temperature. gain tc is expressed in ppm fsr/c. total unadjusted error (tue) total unadjusted e rror is a measure of the output error taking all the various errors into account, namely inl error, offset error, gain error, and output drift over supplies, temperature, and time. tue is expressed in % fsr. digital -to - analog glitch impulse digital - to - analog glitch impulse is the impulse inj ected into the analog output when the input code in the dac register changes state, but the output voltage remains constant. it is normally specified as the area of the glitch in nv - sec and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 31. glitch impulse peak amplitude glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the dac register changes state. it is specified as the amplitude of the glitch in mv and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 31. digital feedthrough digital fe edthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not updated. it is specified in nv - sec and measured with a full - scale code change on the data bus. po wer supply sensitivity power supply sensitivity indicates how the output of the dac is affected by changes in the power supply voltage. it is measured by superimposing a 50 hz/60 hz, 200 mv p - p sine wave on the supply voltages and measuring the proportion of the sine wave that transfers to the outputs.
ad5722/ad5732/AD5752 rev. 0 | page 17 of 32 dc crosstalk this is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full - scale output change on one dac while monitoring another dac . it is expressed in lsbs. digital crosstalk digital crosstalk is a measure of the impulse injected into the analog output of one dac from the digital inputs of another dac but is measured when the dac output is not updated. it is specified in nv - sec and m easured with a full - scale code change on the data bus. dac -to - dac crosstalk dac - to - dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and a subsequent output change of another dac. this includes both digi tal and analog crosstalk. it is measured by loading one of the dacs with a full - scale code change (all 0s to all 1s and vice versa) with ldac low and monitoring the output of another dac. the energy of the glitch is expressed in nv - sec .
ad5722/ad5732/AD5752 rev. 0 | page 18 of 32 theory of operation the ad5722/ad5732/AD5752 are dual, 12 - /14 - /16 - bit, serial input, unipolar/bipolar , voltage output dacs. they operate fr om unipolar supply voltages of + 4.5 v to + 16.5 v or bipolar supply voltages of 4.5 v to 16.5 v. in addition, the parts have softwa re - selectable output ranges of + 5 v, + 10 v, + 10.8 v, 5 v, 10 v, and 10.8 v. data is written to the ad5722/ad5732/ AD5752 in a 24 - bit word format via a 3 - wire serial interface. the devices also offer an sdo pin to facilitate daisy - chain ing or readback. the ad5722/ad5732/AD5752 incorporate a power - on reset circuit to ensure that the dac registers pow er up loaded with 0x0000. when powered on, the outputs are clamped to 0 v via a low impedance path. architecture the dac architecture consi sts of a string dac followed by an output amplifier. figure 38 shows a block diagram of the dac architecture. the reference input is buffered before being applied to the dac. gnd resistor string ref (+) ref (?) configurable output amplifier output range control 06467-006 refin dac register v out x figure 38 . dac architectur e block diagram the resistor string structure is shown in figure 39 . it is a string of resistors, each of value r. the code loaded to the dac register determines the node on the string where t he voltage is to be tapped off and f ed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. r r r r r t o output amplifier refin 06467-007 figure 39 . resistor string structure output amplifiers the output amplifiers are capable of generating both unipolar and bipolar output voltages. they are capable of driving a load of 2 k ? in parallel with 4 000 pf to gnd. the source and sink capabilities of the output amplifiers can be seen i n figure 26. the slew rate is 3 . 5 v/s with a full - scale settling time of 10 s. reference buffers the ad5722/ad5732/AD5752 require an external reference source. the reference input has an input range of 2 v to 3 v , with 2.5 v for specified performance. this input voltage is then buffered before it is applied to the dac cores. serial interface the ad5722/ad5732/AD5752 are controlled over a versatile 3 - wire serial interface that operates at clock rates up to 30 mhz. it is compa tible with s pi , qspi?, microwire?, and dsp standards. input shift register the input shift register is 24 bits wide. data is loaded into the device msb first as a 24 - bit word under the control of a serial clock input, sclk. the input register consists of a read/write bit, three register select bits, three dac address bits, and 16 data bits. the timing diagram for this operation is shown in figure 2 .
ad5722/ad5732/AD5752 rev. 0 | page 19 of 32 standalone operation the serial interface works with both a continuous and noncon - tinuous serial clock. a continuous sclk source can be used only if sync is held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and sync must be taken high after the final clock to latch the data. the first falling edge of sync starts the write cycle. exactly 24 falling clock edges must be applied to sclk before sync is brought high again. if sync is brought high before the 24 th falling sclk edge, the data written is invalid. if more than 24 falling sclk edges are applied before sync is brought high, the input data is also invalid. th e input register addressed is updated on the rising edge of sync . for another serial transfer to take place, sync must be brought low again. after the end of the serial data transfer, data is automatically tran sferred from the input shift register to the addressed register. when the data has been transferred into the chosen register of the addressed dac, all dac registers and outputs can be updated by taking ldac low while * additional pins omitted for clarity. 68hc11 * miso sdin sclk mosi sck pc7 pc6 sdo sclk sdo sclk sdo sdin sdin sync sync sync ldac ldac ldac ad5722/ ad5732/ AD5752* ad5722/ ad5732/ AD5752* ad5722/ ad5732/ AD5752* 06467-008 sync is high. figure 40 . daisy chaining the ad5722/ad5732/AD5752 daisy - chain operation for systems that contain several devices, the sdo pin can be used to daisy - chain several devices together. d aisy - chain mode can be use ful in system diagnostics and in reducing the number of serial interface lines. the first falling edge of sync starts the write cycle. sclk is continuously applied to the input shift register when sync is low. if more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting the sdo of the first device to the sdin in put of the next device in the chain, a multidevice interface is constructed. each device in the system requires 24 clock pulses. therefore, the total number of clock cycles must equal 24 n, where n is the total number of ad5722/ad5732/AD5752 devices in t he chain. when the serial transfer to all devices is complete, sync is taken high. this latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. the seri al clock can be a continuous or a gated clock. a continuous sclk source can only be used if sync is held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and sync readback operation must be taken high after the final clock to latch the data. readback mode is invoked by setting the r/ w bit = 1 in the write operation to the serial input shift register. ( if the sdo output is disabled via the sdo disable bit in the control register, it is automatically enabled for the duration of the read operation , after which it is disabled again . ) with r/ figure 4 w = 1, bit a2 to bit a0 , in association with bit reg2 to bit reg0 , select the register to be read. the remaining data bits in the write sequence are dont care bits. during the next spi write, the data appearing on the sdo output contain s the data from the previously addressed register. for a read of a single register, the nop command can be used in clocking out the data from the selected register on sdo. the readback diagram in shows the readback sequence. f or example, to read back the dac register of channel a , the following sequence should be implemented: 1. write 0x800000 to the ad5722/ad5732/AD5752 input reg ister. this configures the part for read mode with the dac register of channel a selected. note that all the data bits, db15 to db0, are dont care bits. 2. f ollow this with a second write, a nop condition, 0x180000. during this write, the data from the register is clocked out on the sdo line.
ad5722/ad5732/AD5752 rev. 0 | page 20 of 32 load dac ( ldac after data has been transferred into the input register of the dacs, there are two ways to update the dac registers and dac outputs. depending on the status of both ) sync and sy n c sc l k v out x dac register i n t er f a c e l o gi c o u t p u t a mp l i f i er l da c sd o sd i n refin input register 12-/14-/16-bit dac 06467-009 ldac , one of two update modes is selected : individual dac updating or simultaneous updating of all dacs. figure 41 . simplified diagram of input loading circuitry for one dac individual dac updating in this mode, ldac is held low while data is clocked into the input shift register. the addressed dac output is updated on the rising edge of simultaneous updating of all dacs sync . in this mode, ldac is held high while data is clocked into the input shift register. all dac outputs are asynchronously updated by taking ldac low after sync has been taken high. the update now occurs on the falling edge of asynchronous clear ( ldac . clr ) clr is an active low clear that allo ws the outputs to be cleared to either zero - scale code or midscale code. the clear code value is user - selectable via the clr select bit of the control register (see the control register section). it is necessary to maintain clr low for a minimum amount of time to complete the operation (see figure 2 ) . when the clr signal is returned high, the output remains at the cleared value until a new value is programme d. the outputs cannot be updated with a new value while the configuring the ad57 22/ad5732/AD5752 clr pin is low. a clear operation can also be performed via the clear command in the control register. w hen the power supplies are app lied to the ad5722/ad5732/ AD5752, the power - on reset circuit ensures that all registers default to 0 . this places all channels in power - down mode. the first communication to the ad5722/ad5732/AD5752 should be to set the required output range on all channe ls ( the default range i s the 5 v unipolar range) by writing to the output range select register. the user should then write to the power control register to power on the required channels. to program an output value on a channel, that channel must first be powered up; any writes to a channel while it is in power - down mode are ignored. the ad5722/ ad5732/AD5752 operate with a wide power supply range. it is important that the p ower supply applied to the part s provide adequate headroom to support the chosen ou tput ranges. transfer function table 7 to table 15 show the relationships of the ideal input code to output voltage for the AD5752, ad5732, and ad5722, respectively, for all output voltage ranges. for unipolar output ranges, the data coding is straight binary. for bipolar output ranges, the data coding is user selectable via the bin/ 2scomp ? ? ? ? ? ? = n refin out d gain v v 2 pin and can be either offset binary or twos complement. for a unipolar output range, the o utput voltage expression is given by for a bipolar output range, the output voltage expression is given by 2 2 refin n refin out v gain d gain v v ? ? ? ? ? ? ? = where: d is the decimal equivalent of the code loaded to the dac. n is the bit resolution of the dac. v refin is the reference voltage applied at the refin pin. gain is an internal gain whose value depends on the output range selected by the user , as shown in table 6 . table 6 . inter nal gain values output range (v) gain value +5 2 +10 4 +10.8 4.32 5 4 10 8 10.8 8.64
ad5722/ad5732/AD5752 rev. 0 | page 21 of 32 ideal output voltage to input code relationship AD5752 table 7 . bipolar output, offset binary coding digital input analog output msb lsb 5 v output ran ge 10 v output range 10.8 v output range 1111 1111 1111 1111 +2 refin (32 , 767/32 , 768) +4 refin (32 , 767/32 , 768) +4.32 refin (32 , 767/32 , 768) 1111 1111 1111 1110 +2 refin (32 , 766/32 , 768) +4 refin (32 , 766/32 , 768) +4.32 refin (32 , 766 /32 , 768) 1000 0000 0000 0001 +2 refin (1/32 , 768) +4 refin (1/32 , 768) +4.32 refin (1/32 , 768) 1000 0000 0000 0000 0 v 0 v 0 v 0111 1111 1111 1111 ?2 refin (1/32 , 768) ?4 refin (1/32 , 768) ?4.32 refin (32 , 766/32 , 768) 0000 0000 0000 0001 ?2 refin (32 , 766/32 , 768) ?4 refin (32 , 766/32 , 768) ?4.32 refin (32 , 766/32 , 768) 0000 0000 0000 0000 ?2 refin (32 , 767/32 , 768 ?4 refin (32 , 767/32 , 768) ?4.32 refin (32 , 767/32 , 768) table 8 . bipolar output, twos complement coding digital input analog output msb lsb 5 v output range 10 v output range 10.8 v output range 0111 1111 1111 1111 +2 refin (32 , 767/32 , 768) +4 refin (32 , 767/32 , 768) +4.32 refin (32 , 767/32 , 7 68) 0111 1111 1111 1110 +2 refin (32 , 766/32 , 768) +4 refin (32 , 766/32 , 768) +4.32 refin (32 , 766/32 , 768) 0000 0000 0000 0001 +2 refin (1/32 , 768) +4 refin (1/32 , 768) +4.32 refin (1/32 , 768) 0000 0000 0000 0000 0 v 0 v 0 v 1111 1111 1111 1111 ?2 refin (1/32 , 768) ?4 refin (1/32 , 768) ?4.32 refin (1/32 , 768) 1000 0000 0000 0001 ?2 refin (32 , 766/32 , 768) ?4 refin (32 , 766/32 , 768) ?4.32 refin (32 , 766/32 , 768) 1000 0000 0000 0000 ?2 refin (32 , 767/32 , 768) ?4 refin (32 , 767/32 , 768) ?4.32 refin (32 , 767/32 , 768) table 9 . unipolar output, straight binary coding digital input analog output msb lsb +5 v output range +10 v output range +10.8 v output range 111 1 1111 1111 1111 +2 refin (65 , 535/65 , 536) +4 refin (65 , 535/65 , 536) +4.32 refin (65 , 535/65 , 536) 1111 1111 1111 1110 +2 refin (65 , 534/65 , 536) +4 refin (65 , 534/65 , 536) +4.32 refin (65 , 534/65 , 536) 1000 0000 0000 0001 +2 refin (32 , 769/65 , 536) +4 refin (32 , 769/65 , 536) +4.32 refin (32 , 769/65 , 536) 1000 0000 0000 0000 +2 refin (32 , 768/65 , 536) +4 refin (32 , 768/65 , 536) +4.32 refin (32 , 768/65 , 536) 0111 1111 1111 1111 +2 refin (32 , 767/65 , 536) +4 re fin (32 , 767/65 , 536) +4.32 refin (32 , 767/65 , 536) 0000 0000 0000 0001 +2 refin (1/65 , 536) +4 refin (1/65 , 536) +4.32 refin (1/65 , 536) 0000 0000 0000 0000 0 v 0 v 0 v
ad5722/ad5732/AD5752 rev. 0 | page 22 of 32 ideal output voltage to input code relationship ad5732 table 10 . bipolar output, offset binary coding digital input analog output msb lsb 5 v output range 10 v output range 10.8 v output range 11 1111 1111 1111 +2 refin (8191/8192) +4 refin (8191/8192) +4.32 refin (8 191/8192) 11 1111 1111 1110 +2 refin (8190/8192) +4 refin (8190/8192) +4.32 refin (8190/8192) 10 0000 0000 0001 +2 refin (1/8192) +4 refin (1/8192) +4 .32 refin (1/8192) 10 0000 0000 0000 0 v 0 v 0 v 01 1111 1111 1 111 ?2 refin (1/8192) ?4 refin (1/8192) ?4.32 refin (1/8192) 00 0000 0000 0001 ?2 refin (8190/8192) ?4 refin (8190/8192) ?4.32 refin (8190/8192) 00 0000 0000 0000 ?2 refin (8191/8191) ?4 refin (8191/8192) ?4.32 refin (8191/8192) table 11 . bipolar output, twos complement coding digital input analog output msb lsb 5 v output range 10 v output range 10.8 v output range 01 1111 1111 1111 +2 refin (8191/8192) +4 refin (8191 /8192) +4.32 refin (8191/8192) 01 1111 1111 1110 +2 refin (8190/8192) +4 refin (8190/8192) +4.32 refin (8190/8192) 00 0000 0000 0001 +2 refin (1/8192) +4 refin (1/8192) +4 .32 refin (1/8192) 00 0000 0000 0000 0 v 0 v 0 v 11 1111 1111 1111 ?2 refin (1/8192) ?4 refin (1/8192) ?4.32 refin (1/8192) 10 0000 0000 0001 ?2 refin (8190/8192) ?4 refin (8190/8192) ?4.32 refin (8190/8192) 10 0000 0000 0000 ?2 refin (8191/8192) ?4 refin (8191/8192) ?4.32 refin (8191/8192) table 12 . unipolar output, straight binary coding digital input analog output msb lsb + 5 v output range + 10 v output range + 10.8 v output range 11 1111 1111 1111 +2 refin (16 , 383/16 , 384) +4 refin (16 , 383/16 , 384) +4.32 refin (16 , 383/16 , 384) 11 1111 1111 1110 +2 refin (16 , 382/16 , 384) +4 refin (16 , 382/16 , 384) +4.32 refin (16 , 382/16 , 384) 10 0000 0000 0001 +2 refin (8193/16 , 384) +4 refi n (8193/16 , 384) +4.32 refin (8193/16 , 384) 10 0000 0000 0000 +2 refin (8192/16 , 384) +4 refin (8192/16 , 384) +4.32 refin (8192/16 , 384) 01 1111 1111 1111 +2 refin (8191/16 , 384) +4 refin (8191/16 , 384) +4.32 refin (8191/16 , 384) 00 0000 0000 0001 +2 refin (1/16 , 384) +4 refin (1/16 , 384) +4.32 refin (1/16 , 384) 00 0000 0000 0000 0 v 0 v 0 v
ad5722/ad5732/AD5752 rev. 0 | page 23 of 32 ideal output voltage to input code relationship ad5722 table 13 . bipolar output, offset b inary coding digital input analog output msb lsb 5 v output range 10 v output range 10.8 v output range 1111 1111 1111 +2 refin (2047/2048) +4 refin (2047/2048) +4.32 refin (2047/2048) 1111 1111 1110 +2 refin (2046/2048) +4 refin (2046/2048) +4.32 refin (2046/2048) 1000 0000 0001 +2 refin (1/2048) +4 refin (1/2048) +4 .32 refin (1/2048) 1000 0000 0000 0 v 0 v 0 v 0111 1111 1111 ?2 refin (1/2048) ?4 refin (1/2048) ?4.32 refin (1/2048) 0000 0000 0001 ?2 refin (2046/2048) ?4 refin (2046/2048) ?4.32 refin (2046/2048) 0000 0000 0000 ?2 refin (2047/2047) ?4 refin (2047/2048) ?4.32 refin (2047/2048) table 14 . bipolar output, twos co mplement coding digital input analog output msb lsb 5 v output range 10 v output range 10.8 v output range 0111 1111 1111 +2 refin (2047/2048) +4 refin (2047/2048) +4.32 refin (2047/2048) 0111 1111 1110 +2 refin (2046/2048) +4 refi n (2046/2048) +4.32 refin (2046/2048) 0000 0000 0001 +2 refin (1/2048) +4 refin (1/2048) +4 .32 refin (1/2048) 0000 0000 0000 0 v 0 v 0 v 1111 1111 1111 ?2 refin (1/2048) ?4 refin (1/2048) ?4.32 refin (1/2048) 1000 0000 0001 ?2 refin (2046/2048) ?4 refin (2046/2048) ?4.32 refin (2046/2048) 1000 0000 0000 ?2 refin (2047/2048) ?4 refin (2047/2048) ?4.32 refin (2047/2048) table 15 . unipolar output, straight binary coding digital input analog output msb lsb +5 v output range +10 v output range +10.8 v output range 1111 1111 1111 +2 refin (4095/4096) +4 refin (4095/4096) +4.3 2 refin (4095/4096) 1111 1111 1110 +2 refin (4094/4096) +4 refin (4094/4096) +4.32 refin (4094/4096) 1000 0000 0001 +2 refin (2049/4096) +4 refin (2049/4096) +4.32 refin (2049/4096) 1000 0000 0000 +2 refin (2 048/4096) +4 refin (2048/4096) +4.32 refin (2048/4096) 0111 1111 1111 +2 refin (2047/4096) +4 refin (2047/4096) +4.32 refin (2047/4096) 0000 0000 0001 +2 refin (1/4096) +4 refin (1/4096) + 4.32 refin (1/4096) 0000 0000 0000 0 v 0 v 0 v
ad5722/ad5732/AD5752 rev. 0 | page 24 of 32 input s hift register the input shift register is 24 bits wide and consists of a read/write bit (r/ w table 16. input register format ), a reserved bit ( zero ) that must always be set to 0, three register select bits (reg 0 , reg 1, reg2 ), th ree dac address bits (a2, a1, a0), and 16 data bits ( data ). the register data is clocked in msb first on the sdin pin. table 16 sh ow s the register format , and table 17 describes the function of each bit i n the register. all registers are read/write registers. msb lsb db23 db22 db21 db20 db19 db18 db17 db16 db15 to db0 r/ w zero reg2 reg1 reg0 a2 a1 a0 data table 17 . input register bit functions bit mnemonic description r/ w indicates a read from or a write to the addressed register. reg2, reg1, reg0 used in association with the address bits to determine if a write operation is to the dac register, the output range select register, the power control register , or the control register. reg2 reg1 reg0 function 0 0 0 dac r egister 0 0 1 output r ange s elect r egister 0 1 0 power c ontrol r egister 0 1 1 control r egister a2, a1, a0 these dac address bits are used to decode the dac channels. a2 a1 a0 channel address 0 0 0 dac a 0 1 0 dac b 1 0 0 both dacs data data bits.
ad5722/ad5732/AD5752 rev. 0 | page 25 of 32 dac register the dac register is addressed by setting the three reg bits to 000. the dac addre ss bits select the dac channel in which the data transfer is to take place (see table 17 ). the data bits are in positions db15 to db0 for the AD5752 (see table 18 ), db15 to db2 for the ad5732 (see table 19) , and db15 t o db4 for the ad5722 (see table 20) . table 18 . programmi ng the AD5752 dac register msb lsb r/ w zero reg2 reg1 reg0 a2 a1 a0 db15 to db0 0 0 0 0 0 dac a ddress 16-b it dac d ata table 19 . programming the ad5732 dac register msb lsb r/ w zero reg2 reg1 reg0 a2 a1 a0 db15 to db2 db1 db0 0 0 0 0 0 dac a ddress 14-b it dac d ata x x t able 20 . programming the ad5722 dac register msb lsb r/ w zero reg2 reg1 reg0 a2 a1 a0 db15 to db4 db3 db2 db1 db0 0 0 0 0 0 dac a ddress 12-b it dac d ata x x x x output range select register the o utput range select register is addressed by setting the three reg bits to 001. the dac address bit s select the dac channel , and the range bits (r2, r1, r0) select the required output range (see table 21 and table 22) . table 21 . programming the required output range msb lsb r/ w zero reg2 reg1 reg0 a2 a1 a0 db15 to db3 db2 db1 db0 0 0 0 0 1 dac a ddress dont c are r2 r1 r0 table 22 . output range options r2 r1 r0 output range (v) 0 0 0 + 5 0 0 1 + 10 0 1 0 + 10.8 0 1 1 5 1 0 0 10 1 0 1 10.8
ad5722/ad5732/AD5752 rev. 0 | page 26 of 32 control register the control register is addressed by setting the three reg bits to 011. the value written to the address and da ta bits determines the control function selected. the control register options are shown in table 23 and table 24. table 23. programming the control register msb lsb r/ w zero reg2 reg1 reg0 a2 a1 a0 db15 to db4 db3 db2 db1 db0 0 0 0 1 1 0 0 0 n o p, d ata = d ont c are 0 0 0 1 1 0 0 1 dont c are tsd enable clamp enable clr select sdo disable 0 0 0 1 1 1 0 0 clear , d ata = d ont c are 0 0 0 1 1 1 0 1 load , d ata = d ont c are table 24 . explanation of control register options option description nop no operation instruction used in readback operations. clear addressing this function sets the dac registers to the clear code an d updates the outputs. load addressing this function updates the dac registers and , consequently, the dac outputs. sdo disable set by the user to disable the sdo output. cleared by the user to enable the sdo output (default). clr select see table 25 for a description of the clr select operation. clamp enable set by the use r to en able the current - limit clamp. the channel does not power down up on detection of an overcurrent; the current is clamped at 20 ma (default). cleared by the user to dis able the current - limit clamp. the channel powers down up on detection of an overcurrent. tsd enable set by the user to enable the thermal shutdown feature. cleared by the user t o disable the thermal shutdown feature (default). table 25 . clr select options output clr value clr select setting unipolar output range bipolar output range 0 0 v 0 v 1 mids cale negative f ull - s cale power control regist er the power control regist er is addressed by setting the three reg bits to 010. this register allows the user to control and determine the power and thermal status of the ad5722/ad5732/AD5752. the power control r egister options are shown in table 26 and table 27. table 26. programming the power control register msb lsb r/ w zero reg2 reg1 reg0 a2 a1 a0 db15 to db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 0 x 0 oc b x oc a x tsd x x pu b x pu a table 27. power control register functions option description pu a dac a p ower -u p. when set, this bit places dac a in normal operating mode. when cleared, this bit places dac a in power - down mode (default). if the clamp enable bi t of the control register is cleared , dac a power s d own automatically up on detection of an overcurrent and pu a is cleared to reflect this. pu b dac b p ower -u p. when set, this bit places dac b in normal operating mode. when cleared, this bit places dac b in power - down mode (default). if the clamp enable bit of the control register is cleared , dac a power s d own automa tically up on detection of an over current and pu a is cleared to reflect this. tsd thermal s hutdown a lert ( r ead -o nly b it ) . in the event of an o vertemperature situation, both dacs are powered down and this bit is set. oc a dac a o vercurrent a lert ( r ead - o nly b it ) . in the event of an overcurrent situation on dac a, this bit is set. oc b dac b o vercurren t a lert ( r ead - o nly b it ) . in the event of an ove rcurrent situation on dac b, this bit is set.
ad5722/ad5732/AD5752 rev. 0 | page 27 of 32 design features analog output control in many industrial process control applications, it is vital that the output voltage be controlled during power-up. when the supply voltages change during power-up, the v out x pins are clamped to 0 v via a low impedance path (approximately 4 k). to prevent the output amplifiers from being shorted to 0 v during this time, transmission gate g1 is also opened (see figure 42). these conditions are maintained until the power supplies have stabilized and a valid word is written to a dac register. at this time, g2 opens and g1 closes. v out a g1 g2 voltage monitor and control 0 6467-010 figure 42. analog output control circuitry power-down mode each dac channel of the ad5722/ad5732/AD5752 can be individually powered down. by default, all channels are in power-down mode. the power status is controlled by the power control register (see table 26 and table 27 for details). when a channel is in power-down mode, its output pin is clamped to ground through a resistance of approximately 4 k, and the output of the amplifier is disconnected from the output pin. overcurrent protection each dac channel of the ad5722/ad5732/AD5752 incorporates individual overcurrent protection. the user has two options for the configuration of the overcurrent protection: constant current clamp or automatic channel power-down. the configuration of the overcurrent protection is selected via the clamp enable bit in the control register. constant current clamp (clamp enable = 1) if a short circuit occurs in this configuration, the current is clamped at 20 ma. this event is signaled to the user by the setting of the appropriate overcurrent (oc x ) bit in the power control register. upon removal of the short-circuit fault, the oc x bit is cleared. automatic channel power-down (clamp enable = 0) if a short circuit occurs in this configuration, the shorted channel powers down and its output is clamped to ground via a resistance of approximately 4 k. at this time, the output of the amplifier is disconnected from the output pin. the short-circuit event is signaled to the user via the overcurrent (oc x ) bits, and the power-up (pu x ) bits indicate which dacs have powered down. after the fault is rectified, the channels can be powered up again by setting the pu x bits. thermal shutdown the ad5722/ad5732/AD5752 incorporate a thermal shutdown feature that automatically shuts down the device if the core temperature exceeds approximately 150c. the thermal shutdown feature is disabled by default and can be enabled via the tsd enable bit of the control register. in the event of a thermal shutdown, the tsd bit of the power control register is set.
ad5722/ad5732/AD5752 rev. 0 | page 28 of 32 applications informa tion + 5 v/5 v o peration when operating fr om a single +5 v supply or a dual 5 v supply , an output range of +5 v or 5 v is not achievable because suffi - cient headroom for the output amplifier is not available. in this situation , a reduced reference voltage can be used . for example, a 2 v referenc e voltage produce s an output range of +4 v or 4 v, and the 1 v of headroom is more than enough for full operation. a standard value voltage reference of 2.048 v can be used to produce output ranges of +4.096 v and 4.096 v. layout guidelines in any circ uit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5722/ad5732/AD5752 are mounted should be designed so that the analog and dig ital sections are separated and confined to certain areas of the board. if the ad5722/ad5732/AD5752 are in a system where multiple devices require an agnd - to - dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the ad5722/ad5732/AD5752 should have ample supply bypass - ing of a 10 f capacitor in parallel with a 0.1 f capacitor on each supply located as close to the package as possible, ideally right up against the d evice. the 10 f capacitor is the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi) such as the common ceramic types, which provide a low impedance path to ground at high fr equencies to handle transient currents due to internal logic switching. the power supply lines of the ad5722/ad5732/AD5752 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals , such as a data clock , should be shielded with digital ground to avoid radiating noise to other parts of the board , and they should never be run near the reference inputs. a ground line routed between the sdin and sclk lines helps re duce crosstalk between them ( this is not required on a multilayer board that has a separate ground plane, but separating the lines does help ). it is essential to minimize noise on the refin line because any unwanted signals can couple through to the dac ou tput s. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. t his reduces the effects of feed through on the board. a microstrip technique is by far the best method , but it is not alwa ys possible with a double - sided board. in this technique, the component side of the board is dedicated to a ground plane, and signal traces are placed on the solder side. galvanically isolate d interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common - mode voltages that may occur. the i coupler? family of products from analog devices , inc., provi des voltage isolation in excess of 2.5 kv. the serial loading structure of the ad5722/ad5732/AD5752 make s them ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 43 shows a 4 - channel isolated interface to the ad5722/ad5732/AD5752 using an adum1400 . for further information, visit http://www.analog.com/icouplers . encode decode encode decode encode decode v ia v ib v ic v id v oa v ob v oc v od encode decode a d u m 14 0 0 * microcontroller serial clock out serial data out sync out control out to sclk to sdin to sync to ldac *additional pins omitted for clarity. 06467-011 figure 43 . isolated interface voltage reference se lection to achieve optimum performance from the ad5722/ad5732/ AD5752 over their full operating temperature range, a precision voltage reference must be used. thought should be given to the selection of a pr ecision voltage reference. the voltage applied to the reference inputs is used to provide a buffered positive and negative reference for the dac cores. therefore, any error in the voltage reference is reflected in the outputs of the device. there are four possible sources of error to consider when choosing a voltage reference for high accuracy applications : initial accuracy, temperature coefficient of the output voltage, long - term drift, and output voltage noise. ? initial accuracy error on the outp ut voltage of an external refer ence c an lead to a full - scale error in the dac. t o minimize these errors, a reference with low initial accuracy error specification is preferred. choosing a reference with an output trim adjustment, such as the adr421 , allows a system designer to trim out system errors by setting the reference voltage to a voltage othe r than the nominal. the trim ad justment can also be used to trim out temperature - induced errors . ? the temperat ure coefficient of a reference output voltage affects inl, dnl, and tue. a reference with a tight temperature coefficient specification should be chosen to reduce the dependence of the dac output voltage on ambient conditions. ? long - term drift is a measure of how much the reference output voltage drifts over time. a reference with a tight
ad5722/ad5732/AD5752 rev. 0 | page 29 of 32 long - term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. ? reference output voltage noise needs to be considered i n high accuracy a pplications that hav e relatively low noise budgets. it is important to c ho ose a reference with as low an output noise voltage as practical for the required system resolution . precision voltage references such as the adr431 (xfet ? design) produce low output noi se in the 0.1 hz to 10 hz range . however, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. microprocessor inter facing microprocessor i nterfacing to the ad5722/ad5732/AD5752 is via a serial bus that uses a standard protocol compatible with microcontrollers and dsp processors. the communications channel is a 3 - wire (minimum) interface consisting of a clock signal, a data signal, and a sync hronization signal. the ad5722/ ad 5732/AD5752 require a 24 - bit data - word with data valid on the falling edge of sclk. for all interfaces, the dac output update can be initiated automatically when all the data is clocked in, or it can be performed under th e control of ldac ad5722/ad5732/AD5752 to blackfin ? dsp interface . the contents of the registers can be read using the readback function. figure 44 shows how the ad5722/ad5732/AD5752 can be interfaced to t he analog devices blackfin dsp. the blackfin has an integrated spi port that can be connected directly to the spi pins of the ad5722/ad5732/AD5752 and the programmable i/o pins that can be used to set the state of a digital input such as the ldac sync ad sp -bf531 ad5722/ ad5732/ AD5752 sclk sdin spiselx sck mosi ldac pf10 06467-012 pin. figure 44 . ad5722/ad5732/AD5752 to blackfin interface table 28 . some precision references recommended for use with the ad5722/ad5732/AD5752 part no. initial accuracy (mv max) long - term drif t (ppm typ) temp drift (ppm/c max) 0.1 hz to 10 hz noise (v p - p typ) adr431 1 40 3 3.5 adr421 1 50 3 1.75 adr03 2.5 50 3 6 adr291 2 50 8 8 ad780 1 20 3 4
ad5722/ad5732/AD5752 rev. 0 | page 30 of 32 outline dimensions compliant t o jedec s t andards mo-153-adt 061708- a 24 13 12 1 6.40 bsc 0.15 0.05 0.10 coplanarit y t op view exposed p ad (pins up) bot t om view 4.50 4.40 4.30 7.90 7.80 7.70 1.20 max 1.05 1.00 0.80 0.65 bsc 0.30 0.19 sea ting plane 0.20 0.09 8 0 0.75 0.60 0.45 5.02 5.00 4.95 3.25 3.20 3.15 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 45 . 24 - lead thin shrink small outline package, exposed pad [tss op_ep] (re - 24) dimensions shown in millimeters ordering guide model resolution (bits) temperature range inl tue (% fsr) package description package option ad5722arez 1 12 ?40c to +85c 1 lsb 0.3 24- lead tssop_ep re -24 ad5722arez - reel7 1 12 ?40c to +85c 1 lsb 0.3 24- lead tssop_ep re -24 ad5732arez 1 14 ?40c to +85c 4 lsb 0.3 24- lead tssop_ep re -24 ad5732arez - reel7 1 14 ?40c to +85c 4 lsb 0.3 24- lead t ssop_ep re -24 AD5752brez 1 16 ?40c to 85c 16 lsb 0.1 24- lead tssop_ep re -24 AD5752brez - reel7 1 16 ?40c to 85c 16 lsb 0.1 24- lead tssop_ep re -24 AD5752arez 1 1 6 ?40c to +85c 16 lsb 0.3 24- lead tssop_ep re -24 AD5752arez - reel7 1 16 ?40c to +85c 16 lsb 0.3 24- lead tssop_ep re -24 1 z = rohs compliant part.
ad5722/ad5732/AD5752 rev. 0 | page 31 of 32 notes
ad5722/ad5732/AD5752 rev. 0 | page 32 of 32 ? 2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06467 - 0 - 10/08(0) notes

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